DocumentCode
2398880
Title
A 23ns 1Mbit BiCMOS DRAM
Author
Yanagisawa, Kazumasa ; Kitsukawa, Goro ; Kobayashi, Yutaka ; Kinoshita, Yoshitaka ; Ohta, Talsuyuki ; Udagawa, Tetsu ; Ishii, Kyoko ; Miwa, Hitoshi ; Miyazawa, Hiroyuki ; Ouchi, Yoshiaki ; Tsukada, Hiromi ; Matsumoto, Tetsuro ; Itoh, Kiyoo
Author_Institution
Hitachi Device Dev. Center, Tokyo, Japan
fYear
1989
fDate
20-22 Sept. 1989
Firstpage
184
Lastpage
187
Abstract
A 1Mbit, BiCMOS DRAM, having a 23ns access time, has been developed using direct sensing technique combined with high sensitive bipolar circuits. This chip was verified to have high speed characteristics, while maintaining a wide operating margin. In spite of 1.3μm level, this DRAM realizes a competing high-speed access time and a relatively small chip size.
Keywords
BiCMOS memory circuits; DRAM chips; bipolar integrated circuits; BiCMOS DRAM; direct sensing; high sensitive bipolar circuits; high-speed access time; storage capacity 1 Mbit; time 23 ns; BiCMOS integrated circuits; CMOS process; Clocks; Differential amplifiers; Laboratories; Random access memory; Semiconductor device measurement; Tellurium; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location
Vienna
Print_ISBN
3-85403-101-7
Type
conf
DOI
10.1109/ESSCIRC.1989.5468110
Filename
5468110
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