• DocumentCode
    2399595
  • Title

    Parallel Decomposition in Logic Synthesis

  • Author

    Jasiñski, Krzysztof ; Luba, Tadeusz ; Kalinowski, Jordan

  • Author_Institution
    Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw, Poland
  • fYear
    1989
  • fDate
    20-22 Sept. 1989
  • Firstpage
    113
  • Lastpage
    116
  • Abstract
    In this paper a new approach to logic synthesis in VLSI design, based on parallel decomposition, is proposed. The idea is to use an effective method for multiple-output function reduction to select a decomposition that yields minimal silicon area in the final implementation. Experimental results and assessment of this synthesis method are provided.
  • Keywords
    VLSI; elemental semiconductors; integrated circuit yield; logic design; silicon; Si; VLSI design; logic synthesis; minimal silicon area; multiple-output function reduction; parallel decomposition; yield decomposition; Boolean functions; Decoding; Input variables; Logic design; Logic devices; Logic gates; Minimization; Programmable logic arrays; Silicon; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
  • Conference_Location
    Vienna
  • Print_ISBN
    3-85403-101-7
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.1989.5468151
  • Filename
    5468151
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2399595