Technology independent VLSI-Design using Bit Level self-timed circuits

Author

Heer, C. ; Aumann, O.

Author_Institution

Abt. fur Allgemeine Elektrotechnik und Mikroelektron., Univ. Ulm, Ulm, Germany

fYear

1992

fDate

21-23 Sept. 1992

Firstpage

303

Lastpage

306

Abstract

In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5μm-and a 0,8μm-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5μm) up to 100 MHz (0,8μm) have been measured for self-timed asynchronous test circuits.

Keywords

CMOS integrated circuits; VLSI; clocks; integrated circuit design; synchronisation; CMOS-technology; bit level self-timed asynchronous circuits; circuit speed-up; clock frequencies; device performance enhancement; frequency 35 MHz to 100 MHz; handshake cycle; size 1 mum; size 5 mum; size 8 mum; synchronization; technology independent VLSI-design; Adders; Asynchronous communication; Circuit synthesis; Circuit testing; Clocks; Delay; Frequency synchronization; Latches; Logic; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Conference_Location

Copenhagen

Print_ISBN

87-984232-0-7

Type

conf

DOI

10.1109/ESSCIRC.1992.5468165

Filename

5468165