Optimizing a 32nm development fab´s HOL defect pareto using iDO and eADC

Author

Boye, C.A. ; Yathapu, N. ; Kini, S.

Author_Institution

IBM Corp., Albany, NY, USA

fYear

2009

fDate

10-12 May 2009

Firstpage

38

Lastpage

40

Abstract

This paper presents a methodology for optimizing a fab defect pareto for 32 nm Health of Line (HOL). HOL involves running a selected product as a means of generating defect baseline paretos and electrical test for key process sectors. Optimizing HOL pareto consists of increasing the capture of key yield limiting defects and minimizing the capture of non yield limiting defects. This was achieved by implementing smart binning (iDO) on the BF inspection system in conjunction with auto defect classification (eADC) on the SEM review tool.

Keywords

Pareto optimisation; inspection; scanning electron microscopy; BF inspection system; SEM; autodefect classification; defect baseline paretos; electrical test; fab HOL defect pareto; health-of-line; implementing smart binning; key process sectors; key yield limiting defects; size 32 nm; Apertures; Classification tree analysis; Inspection; Manufacturing; Pareto optimization; Sampling methods; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2009. ASMC '09. IEEE/SEMI

Conference_Location

Berlin

ISSN

1078-8743

Print_ISBN

978-1-4244-3614-9

Electronic_ISBN

1078-8743

Type

conf

DOI

10.1109/ASMC.2009.5155949

Filename

5155949