Unified fault management using Logic Built-In Self-Test and logic bitmap

At-speed Logic BIST(Built-In Self-Test) has been embedded to the latest Cisco ASICs (Application Specific Integrated Circuit) and the test can be run on ATE (automatic test equipment) at probe and final test, as well as in-system during diagnostics, manufacturing, and even in the field. A fail state can be captured via JTAG interface. This paper presents a unified method of capturing LBIST failing flops for diagnostics. This allows failure analysis via scan-chain, design hierarchical, or physical view for fault isolation, yield, and maverick lot optimization. Most importantly, it provides a direct comparison of system test failure information with probe and final test.