Multi-level fault simulation of digital systems on decision diagrams

Author

Ubar, Raimund ; Raik, Jaan ; Ivask, Eero ; Brik, Marina

Author_Institution

Tallinn Tech. Univ., Estonia

fYear

2002

fDate

2002

Firstpage

86

Lastpage

91

Abstract

A new method for hierarchical fault simulation based on multi-level decision diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows one to reduce time expenses in the comparison to traditional gate-level fault simulation approach

Keywords

decision diagrams; fault simulation; high level synthesis; logic simulation; multivalued logic; RT level structure; decision diagrams; digital systems; gate-level descriptions; hierarchical fault simulation; multi-level fault simulation; register transfer level information; representation levels; time expenses; uniform model; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Data structures; Digital systems; Fault diagnosis; Registers; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994594

Filename

994594