Design and simulation of high level low power 7T SRAM cell using various process & circuit techniques

Low power memory is required today most priority with also high stability. The power is most important factor for today technology so the power reduction for one cell is vital role in memory design techniques. In this paper we introduced some design circuit techniques for low power design. Leakage current in standby mode is the major part of power loss. We concentrate on the technique that to reduced the leakage current in standby mode.