High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips

VLSI chips suffer from exaggerated clock skew problems when the clock rate reaches several hundred MHz. To overcome this problem, back-propagating clock signals, the use of which is usually avoided (due to extended clock period) but known to be safe, can be exploited, resulting in a new pipelining method. We named this Counterflow-Clocked (C²) Pipelining. The major advantages of this new method are: easier distribution of high speed clocks, shorter clock period due to the absence of global clock signals, natural use of dynamic latches, less internally generated noise due to uniformly distributed latch operations, etc. Composition rules were developed. The use of these rules enabled us to build a system with two-dimensional data-flow in C ² pipelining employing a tree of inverter chains for clock distribution. C² pipelining was used to design an HDTV chip set with several design innovations, demonstrating the applicability and viability of the technology. This paper introduces C² pipelining and discusses its usefulness and limitations to build large and high speed VLSI chips. It also presents the design of an image compression chip set to implement subband vector quantization that can handle HDTV data rates with reasonable VLSI chip sizes