A GaAs BiFET LSI technology

Author

Ho, W.J. ; Chang, M.F. ; Beccue, S.M. ; Zampardi, P.J. ; Yu, J. ; Sailer, A. ; Pierson, R.L. ; Wang, W.C.

Author_Institution

Sci. Center, Rockwell Int. Corp., Thousand Oaks, CA, USA

fYear

1994

fDate

16-19 Oct. 1994

Firstpage

47

Lastpage

50

Abstract

A GaAs BiFET LSI technology has been successfully developed for low power, mixed mode communication circuit applications. The direct placement of the FET on the HBT emitter cap layer simplifies the device epitaxial growth and process integration. High integration levels and functional circuit yield have been achieved. Excellent HBT and FET characteristics have been produced with the noise figure of the FETs comparable to those of traditional MESFETs, enabling them to perform well in front end receiver applications. Through this technology, several LSI circuits, including 32-bit by 2-bit shift registers and a single-chip DRFM have been successfully demonstrated.

Keywords

III-V semiconductors; gallium arsenide; integrated circuit noise; integrated circuit technology; integrated circuit yield; large scale integration; monolithic integrated circuits; 2 bit; 32 bit; FET; GaAs; GaAs BiFET LSI technology; HBT; MESFET; epitaxial growth; front end receiver; low power mixed mode communication circuit; noise figure; process integration; shift registers; single-chip DRFM; yield; FET integrated circuits; Gallium arsenide; Heterojunction bipolar transistors; Integrated circuit noise; Large scale integration; MESFETs; Shift registers; Space technology; Substrates; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1994. Technical Digest 1994., 16th Annual

Conference_Location

Phildelphia, PA, USA

ISSN

1064-7775

Print_ISBN

0-7803-1975-3

Type

conf

DOI

10.1109/GAAS.1994.636916

Filename

636916