A VLSI-processor for the generation of the hierarchical structure code in real time

Author

Bilau, N. ; Schnusenberg, J. ; Hartmann, G. ; Siggelkow, A. ; Schwederski, T.

Author_Institution

Paderborn Univ., Germany

fYear

1993

fDate

15-17 Dec 1993

Firstpage

67

Lastpage

76

Abstract

The hierarchical structure code (HSC) is a data structure encoding all the structural information of images at different levels of resolution. Continuity between neighboring edge elements, line elements, and region elements is verified by a hierarchical linking procedure mapping continuous structures onto code-trees. This HSC data structure allows top down analysis and proved to be very helpful in traffic scene analysis. The HSC data structure is exclusively generated by local operations. Accordingly, the authors could successfully map the encoding procedure onto a special VLSI chip controlled by a set of programmable gate arrays. The chip is based on a sea-of-gates template, the IMS Gate Forest, and a semicustom cell-library and works at a speed of 12.5 frames/sec of 513² images

Keywords

real-time systems; IMS Gate Forest; VLSI chip; VLSI-processor; code-trees; continuous structures; data structure; hierarchical linking procedure; hierarchical structure code; line elements; neighboring edge elements; region elements; sea-of-gates template; semicustom cell-library; structural information; top down analysis; traffic scene analysis; Data structures; Encoding; Humans; Image analysis; Image coding; Image edge detection; Image resolution; Joining processes; Microelectronics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 1993. Proceedings

Conference_Location

New Orleans, LA

Print_ISBN

0-8186-5420-1

Type

conf

DOI

10.1109/CAMP.1993.622459

Filename

622459