LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

Summary form only given. Over the last several years there has been a great deal of excitement about the double-gate (DG) SOI MOSFET as the enabling Si device for the 0.05 μm node and beyond. As a result a number of DG structures have been proposed and analyzed, and several have been experimentally demonstrated. Although these devices are currently being vigorously researched and evolving, most structures are commonly categorized as symmetric (SDG), where both gates are made of the same polysilicon type (usually n⁺) and asymmetric (ADG), where one gate is n⁺ and the other p⁺ type polysilicon. The n⁺ gate SDG is a "normally on" device (negative threshold voltage), and for this and other reasons the favor is currently with the ADG device, although metal gates of appropriate workfunction values are being considered to fine-tune the SDG device. Rather than modify the SDG device at the expense of complicated processing, the authors seek to investigate the possibility of using this intrinsically on structure as a load device for DG-SOI based ratioed logic, with ADG drivers.