DocumentCode
2406395
Title
Surface roughness and device layer thickness for ultra-thin SOI
Author
Current, M.I. ; Malik, I.J. ; Fuerfanger, M. ; Flat, A. ; Sullivan, J. ; Kang, S. ; Kirk, H.R. ; Norcott, M. ; Teoh, D. ; Ong, P. ; Henley, F.J.
Author_Institution
Silicon Genesis Corp., San Jose, CA, USA
fYear
2002
fDate
7-10 Oct 2002
Firstpage
111
Lastpage
112
Abstract
Results for epi-based final surface finishing are reported for ultra-thin (<50 nm device layers) SOI wafers. Near and sub-Angstrom surface roughness over lateral scales up to 10 μm and device layer thickness uniformity range (max-min) of 10% have been achieved for 200 and 300 mm SOI wafers.
Keywords
CMOS integrated circuits; silicon-on-insulator; surface topography; surface treatment; 10 micron; 200 mm; 300 mm; SOI wafers; epi-based final surface finishing; fully-depleted CMOS; surface roughness; thickness uniformity; ultra-thin layers; CMOS integrated circuits; Silicon on insulator technology; Surface treatment;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, IEEE International 2002
Print_ISBN
0-7803-7439-8
Type
conf
DOI
10.1109/SOI.2002.1044440
Filename
1044440
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