An efficient 3-bit-scan multiplier without overlapping bits, and its 64×64 bit implementation

In this paper, we present an efficient 3-bit-scan multiplier without overlapping bits which has good power-delay area trade-offs. Generation of partial product terms in this multiplier is performed in parallel with the multiplication operation. Parallel partial product generation results in a multiplier which is faster than conventional sequential multipliers. The architecture of the 3-bit-scan multiplier without overlapping bits is therefore suitable for synchronous sequential multipliers which are required to operate at low power and at relatively high speed for their area