Efficient macromodeling for on-chip interconnects

The improved T and improved Π models are proposed for on-chip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeling of on-chip distributed RC interconnects. The applications lead to equivalent circuit models for on-chip interconnects, which are represented by the improved T and improved Π models. By matching the first three moments of an open-ended interconnect, the improved Π model with AWE is consequently obtained, which retains the symmetric structure. The new models for distributed RC interconnects are independent of CMOS gates, and therefore can be directly incorporated into SPICE frames. Numerical experiments show that for current feature sizes, the improved T and improved Π modeling methods can be used to accurately evaluate on-chip interconnect effects, while the computational costs are comparable to the original T and original Π modeling. The presented macromodeling approaches are useful for quick simulation and layout optimization