Characterization of flip-chip CMOS ASIC simultaneous switching noise on multilayer organic and ceramic BGA/CGA packages

Author

Libous, James P.

Author_Institution

Adv. CMOS ASIC Technol. Dev., IBM Miroelectron., Endicott, NY, USA

fYear

1998

fDate

26-28 Oct 1998

Firstpage

191

Lastpage

194

Abstract

This paper presents the characterization of flip-chip CMOS ASIC core logic and I/O simultaneous switching noise on several types of high density multilayer organic and ceramic ball grid array (BGA) and column grid array (CGA) packages. The results of time domain simultaneous switching output noise measurements with a CMOS test chip are presented. Core logic switching noise modeling and simulation results are also discussed

Keywords

CMOS logic circuits; application specific integrated circuits; ball grid arrays; ceramic packaging; flip-chip devices; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; time-domain analysis; CMOS test chip; ball grid array; column grid array; core logic switching noise modeling; core logic switching noise simulation; flip-chip CMOS ASIC I/O; flip-chip CMOS ASIC core logic; flip-chip CMOS ASIC simultaneous switching noise; multilayer ceramic BGA packages; multilayer ceramic CGA packages; multilayer organic BGA packages; multilayer organic CGA packages; simultaneous switching noise; time domain simultaneous switching output noise measurements; Application specific integrated circuits; CMOS technology; Ceramics; Circuit noise; Noise reduction; Nonhomogeneous media; Packaging; Testing; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on

Conference_Location

West Point, NY

Print_ISBN

0-7803-4965-2

Type

conf

DOI

10.1109/EPEP.1998.733969

Filename

733969