Delay and power consumption of fault tolerant data busses in VDSM technology

In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of CMOS technology to cause various noise mechanismssuch as power supply noise, crosstalk noise, leakage noise, etc. In VDSM technology distance between the data bus lines is reduced, so coupling capacitance is dominating factor. Unfortunately, in VDSM systems, the coupling capacitance is of magnitude several times larger than the loading capacitance. The coupling capacitance causes logical malfunction, delay faults, and power consumption on long on-chip data buses. An important effect of the coupling capacitance is Cross talk. Crosstalk is mainly dependent on several factors: drive strength, wire length/spacing, edge rate and propagation duration. The crosstalk noise produces from the coupling capacitance. Such faults may affect data on data bus. To avoid this condition and to guarantee signal integrity on the on-chip communication, a fault tolerant bus can be adopted. This could be achieved by implementing error-correcting codes (ECCs), providing on-line correction and do not require data retransmission. The 4,8,16, and 32-bit data bus is implemented in 180 nm, 120 nm, and 65 nm technologies using Bsim4 model. For reliable transmission of the data ECC techniques is placed on the data bus. We employed a Hamming code and Dual rail as ECC for 4,8,16 and 32-bit fault tolerant data bus. This is implemented in 180 nm, 120 nm and 65 nm technology. The simulation results show that Average power varies from 0.737 mW to 0.176 mW, and Maximum delay varies from 0.143 nsec to 0.077 nsec, for hamming 4 bit ECC, Average power varies from 2.135 mW to 0.365 mW and Maximum delay varies from 0.385 nsec to 0.192 nsec for hamming 8 bit ECC, Average power varies from 2.288 mW to 0.377 mW and Maximum delay varies from 0.721 nsec to 0.353 nsec for hamming 16 bit ECC, Average power varies from 3.064 mW to 0.437 mW and Maximum delay varies from 1.562 nsec to 0.796 nsec for hamming 32 bit ECC. The s- - imulation results show that Average power varies from 0.206 mW to 0.0459 mW, and Maximum delay varies from 0.241 nsec to 0.133 nsec, for dual rail 4 bit ECC, Average power varies from 0.417 mW to 0.0768 mW and Maximum delay varies from 0.479 nsec to 0.262 nsec for dual rail 8 bit ECC, Average power varies from 0.726 mW to 0.156 mW and Maximum delay varies from 1.026 nsec to 0.554 nsec for dual rail 16 bit ECC, Average power varies from 0.926 mW to 0.108 mW and Maximum delay varies from 2.129 nsec to 1.145 nsec for dual rail 32 bit ECC respectively.