A novel ESD device structure with fully silicide process for mixed high/low voltage operation

A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1 mum to 65 nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5 KV and MM < 50 V to HBM 4 KV and MM 200 V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.