On mapping of DSP algorithms onto hardware

The authors discuss certain basic computational properties of DSP algorithms. It is shown that classical critical path methods based on signal-flow graphs can be extended to give a better insight into the computational properties of an algorithm and into the scheduling of the arithmetic operations. The relationship between the scheduled operations and the hardware architecture is also discussed. The authors propose a systematic procedure to synthesize optimal architectures. Further, they introduce measures of parallelism, processor utilization, and speed-up factor of an algorithm.<>