DocumentCode
2410496
Title
On modeling cross-talk faults [VLSI circuits]
Author
Zachariah, Sujit T. ; Chang, Yi-Shing ; Kundu, Sandip ; Tirumurti, Chandra
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2003
fDate
2003
Firstpage
490
Lastpage
495
Abstract
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross coupling between interconnects is known to be a prime contributor to such failures. In this paper, we present novel techniques to model and prioritize capacitive cross-talk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on industrial circuits.
Keywords
VLSI; circuit analysis computing; crosstalk; digital integrated circuits; fault diagnosis; integrated circuit modelling; capacitive cross coupling; capacitive cross-talk faults; crosstalk fault modelling; high performance VLSI circuits; interconnects; Circuit noise; Circuit testing; Crosstalk; Frequency; Integrated circuit interconnections; Optical noise; Peer to peer computing; Signal design; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253657
Filename
1253657
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