• DocumentCode
    2410985
  • Title

    CMOS/SOS 16-Bit Parallel Multiplier and Adder-Subtractor

  • Author

    Oldham, H.E.

  • Author_Institution
    GEC Hirst Res. Centre, Wembley, UK
  • fYear
    1980
  • fDate
    22-25 Sept. 1980
  • Firstpage
    196
  • Lastpage
    200
  • Abstract
    Two high performance CMOS/SOS devices for use in digital signal processing applications are described: a 16-bit parallel multiplier featuring a novel logic implementation and a 3 × 8-bit adder-subtractor circuit.
  • Keywords
    CMOS integrated circuits; adders; digital signal processing chips; CMOS-SOS parallel multiplier; adder-subtractor; digital signal processing applications; logic implementation; word length 16 bit; Adders; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Delay; Digital signal processing; Latches; Logic devices; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
  • Conference_Location
    Grenoble
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.1980.5468771
  • Filename
    5468771
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2410985