A P1500-compatible programmable BIST approach for the test of embedded flash memories

Author

Bernardi, P. ; Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M.

Author_Institution

Dipt. di Automatica e Informatica, Politecnico di Torino, Italy

fYear

2003

fDate

2003

Firstpage

720

Lastpage

725

Abstract

In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-a-chip (SoC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architecture to different memory cores. The proposed approach is compatible with the P1500 standard. A case study has been developed and demonstrates the advantages of the proposed core test strategy in terms of area overhead and test application time.

Keywords

built-in self test; flash memories; instruction sets; integrated circuit testing; integrated memory circuits; logic testing; microprocessor chips; system-on-chip; P1500 standard; P1500-compatible BIST approach; SoC environment; area overhead; core test strategy; embedded flash memory testing; instruction set; memory cores; microprocessor-based approach; programmable BIST approach; pseudo-March algorithms; system-on-a-chip environment; test application time; Automatic testing; Built-in self-test; Costs; Design for testability; Flash memory; Logic testing; Random access memory; Software testing; System testing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253692

Filename

1253692