DocumentCode
2413217
Title
Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG
Author
Ichihara, Hideyuki ; Inoue, Tomoo
Author_Institution
Fac. of Inf. Sci., Hiroshima City Univ., Japan
fYear
2003
fDate
2003
Firstpage
1180
Lastpage
1181
Abstract
An existing test generation method with a time-expansion model can achieve high fault efficiency for acyclic sequential circuits. While this model is a combinational circuit, a single stuck-at fault in the original circuit is represented by a multiple one in this model. This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in a time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just a combinational test pattern generation algorithm for single stuck-at faults.
Keywords
automatic test pattern generation; combinational circuits; fault diagnosis; logic testing; sequential circuits; MS-model; acyclic sequential circuit test generation; combinational ATPG; combinational circuit; fault efficiency; multiple stuck-at faults; single stuck-at faults; test pattern generation; test sequence generation; time-expansion model; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Joining processes; Logic functions; Registers; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253790
Filename
1253790
Link To Document