• DocumentCode
    2413261
  • Title

    Evolutionary optimization of Markov sources for pseudo random scan BIST

  • Author

    Polian, Ilia ; Becker, Bernd ; Reddy, Sudhakar M.

  • Author_Institution
    Albert-Ludwigs-Univ., Freiburg Im Breisgau, Germany
  • fYear
    2003
  • fDate
    2003
  • Firstpage
    1184
  • Lastpage
    1185
  • Abstract
    Recent work by Basturkmen et al. (2002) showed that Markov sources lead to scan BIST designs of lower cost compared to earlier proposed methods in scan BIST. However the method presented by Basturkmen et al. utilizes tests generated using a deterministic test generator for target faults in synthesizing the Markov source to generate the tests. The requirement of a deterministic test generator may hinder the use of this procedure in industrial settings since the BIST tool must also include a deterministic ATPG tool that may add to the cost of the BIST tool. In this paper we investigate a procedure to synthesize BIST controllers with Markov sources for test generation using Evolutionary Algorithms (EAs). This allows us to avoid using the deterministic ATPG needed previously. Additionally we do not employ inversion logic used in by Basturkmen et al., thereby potentially reducing the hardware in the BIST controller. Nevertheless, the proposed method achieves close to 100% fault efficiency using far fewer tests than required by pseudo random tests. In this work, similar to that of Basturkmen et al., we employ Markov sources based on finite state machines (FSMs) with transitions controlled by additional inputs. Hence, transition probabilities (TPs) of the FSM are determined by the 1-probability on a corresponding input.
  • Keywords
    Markov processes; automatic test pattern generation; built-in self test; finite state machines; integrated circuit testing; logic testing; probability; BIST controller synthesis; FSM; Markov sources; evolutionary algorithms; evolutionary optimization; finite state machines; pseudo random scan BIST; test generation; transition probabilities; Automatic test pattern generation; Built-in self-test; Circuit faults; Cities and towns; Costs; Electrical fault detection; Evolutionary computation; Fault detection; Phase detection; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2003
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1870-2
  • Type

    conf

  • DOI
    10.1109/DATE.2003.1253792
  • Filename
    1253792