Integration of CMP Modeling in RC Extraction and Timing Flow

As technology scaling progresses into 65 nm and below nodes, on chip variation (OCV) specifically interconnect thickness variation due to chemical mechanical polishing (CMP) becomes relatively larger, as such it needs to be taken into consideration in the post layout RC extraction and timing flow. Traditionally manufacturing effects due to lithography and CMP processes are captured using rule based look up tables. These look up tables are included in the technology file of RC extraction tools. However, due to complex nature of CMP process and design topology, the generic rules can not capture thickness variation accurately. Therefore CMP models are used to generate design specific thickness variation profile, based on the calibrated manufacturing process library. In this paper, we demonstrate that by incorporating CMP model in the post layout RC extraction flow, the thickness variations are reflected more accurately and the capacitance value extracted are different from results obtained using the polynomial equation based approach. As a result, new timing violations are detected with CMP modeling.