A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Author

Suttorp, Thomas ; Langmann, Ulrich

Author_Institution

Ruhr-Univ. Bochum, Bochum

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

277

Lastpage

280

Abstract

A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm². The CDR fulfills the SONET/SDH jitter tolerance requirements at a 2³¹-1 PRBS and a BER of < 10^-12. Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.

Keywords

CMOS integrated circuits; SONET; adaptive equalisers; clocks; multiprocessing systems; optical receivers; synchronisation; BER; CMOS serial-link receiver; PRBS; SONET-SDH jitter tolerance; adaptive equalization; bit rate 10 Gbit/s; chip-to-chip communication; clock recovery; data recovery; digital clock; eye-opening monitoring; integrated circuit fabrication; prototype circuit; size 0.13 mum; standard FR4 substrate; voltage 1.2 V; Adaptive equalizers; CMOS technology; Circuits; Clocks; Jitter; Monitoring; Prototypes; SONET; Synchronous digital hierarchy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405732

Filename

4405732