A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links

Author

Kiaei, Ali ; Matinpour, Babak ; Bahai, Ahmad ; Lee, Thomas H.

Author_Institution

Stanford Univ., Stanford

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

285

Lastpage

288

Abstract

A 10 Gb/s equalizer using both feedforward and decision-feedback equalization is designed for high speed serial-links. The chip is implemented in a standard 0.25 mum SiGe BiCMOS technology with 50 GHz peak f_t, and packaged in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor cancellation, this equalizer achieves a total peak-to-peak jitter of 27 ps and 33 ps for 10" and 20" of copper traces on FR4, respectively. The transmitter uses NRZ signaling with no pre-emphasis.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; decision feedback equalisers; 2-tap post-cursor cancellation; 4-stage feedforward cancellation; BiCMOS technology; LLP package; NRZ signaling; SiGe; backplane communications; bit rate 10 Gbit/s; decision-feedback equalization; equalizer; feedforward equalization; high speed serial links; size 0.25 mum; time 27 ps; time 33 ps; Backplanes; Copper; Decision feedback equalizers; Dielectric losses; Frequency; Intersymbol interference; Jitter; Propagation losses; Semiconductor device packaging; USA Councils; backplane communications; decision-feedback; equalizer; serial-link;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405734

Filename

4405734