• DocumentCode
    2414540
  • Title

    Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization

  • Author

    Kodama, Hiroshi ; Okada, Hiroyuki ; Ishikawa, Hiromu ; Tanaka, Akio

  • Author_Institution
    NEC Corp., Kawasaki
  • fYear
    2007
  • fDate
    16-19 Sept. 2007
  • Firstpage
    349
  • Lastpage
    352
  • Abstract
    To relax the trade-off relationship between tuning range and phase noise, we have developed a new interpolative ring-VCO having a wide control voltage range over which frequency variation is linear. A wide lock-range, low phase noise PLL incorporating this VCO has been fabricated in a 90 nm CMOS process. It successfully operates at from 3.432 to 4.488 GHz (LF-mode) and from 6.600 to 9.240 GHz (HF-mode), with 528 MHz spacing, while drawing 30 to 37 mA from a 1.5 V supply. Measured integrated phase noise is below a targeted 4 degrees in both modes when the reference frequency is 264 MHz and less than 4 degrees in the LF-mode when it is 66 MHz.
  • Keywords
    CMOS integrated circuits; MMIC oscillators; phase locked loops; phase noise; voltage-controlled oscillators; CMOS process; coarse frequency tuning; current 30 mA to 37 mA; frequency 3.432 GHz to 4.488 GHz; frequency 6.600 GHz to 9.240 GHz; frequency linearization; integrated phase noise; interpolative ring-VCO; low phase-noise PLL; size 90 nm; voltage 1.5 V; wide lock-range PLL; Circuit optimization; Clocks; Energy consumption; Frequency conversion; Phase locked loops; Phase noise; Transceivers; Tuning; Voltage control; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-1623-3
  • Electronic_ISBN
    978-1-4244-1623-3
  • Type

    conf

  • DOI
    10.1109/CICC.2007.4405750
  • Filename
    4405750