DocumentCode
2415088
Title
High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications
Author
Kim, Moon-Jung ; Icking, Henrik ; Gossner, Harald ; Lee, Thomas H.
Author_Institution
Stanford Univ., Stanford
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
491
Lastpage
494
Abstract
We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.
Keywords
CMOS integrated circuits; network synthesis; system buses; CMOS process; USB 2.0-compliant; high-voltage-tolerant I/O circuit design; over-voltage tolerance; Breakdown voltage; CMOS process; Circuit synthesis; Circuit testing; Degradation; Firewire; Hot carriers; Protection; Stress; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405779
Filename
4405779
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