PSP-Based Scalable MOS Varactor Model

Author

Victory, James ; Zhu, Z. ; Zhou, Q. ; Wu, W. ; Gildenblat, G. ; Yan, Z. ; Cordovez, J. ; McAndrew, C. ; Anderson, F. ; Paasschens, J.C.J. ; van Langevelde, R. ; Kolev, P. ; Cherne, R. ; Yao, C.

Author_Institution

Jazz Semicond., Newport Beach

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

495

Lastpage

502

Abstract

A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.

Keywords

MIS devices; hardware description languages; semiconductor device models; surface potential; varactors; voltage-controlled oscillators; MOS varactor specific gate current models; PSP-based analytical surface potential charge formulation; PSP-based scalable MOS varactor model; RF simulation; VCO design application; Verilog-A; parasitic modeling; physical geometry; process parameter; Geometry; Hardware design languages; Parasitic capacitance; Q factor; Radio frequency; Robustness; Solid modeling; Varactors; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-0786-6

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405780

Filename

4405780