Design of a low power CMOS class-D amplifier for hearing aids

This work proposes a design of a class-D amplifier for low voltage operation and reduced power consumption, for application in hearing aid devices. Applying compact model equations to the design based on the inversion level guarantees an optimum trade-off among area, power consumption, minimum operation voltage and frequency. The correct operation of the system was verified through simulations of the circuits designed in commercial 0.35 μm technology. Efficiencies over 75%, up to a maximum of 90.6% were achieved for output power greater than one quarter of the maximum power. The power consumption without load is 68 μW at 1.4 V power supply, the minimum operation voltage is 1.1 V, with total harmonic distortion less than 1%. The amplifier active area is around 0.073 mm2.