A phase-error cancellation technique for fast-lock PLL

This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast-lock in analog phase-locked loops (PLLs). Similar as PLL with bandwidth switching control technique, the PLL employing this technique has two operation modes, the fast-lock mode and the normal mode. This PLL works in fast-lock mode during phase and frequency tracking and switches to normal mode after the PLL is almost locked. This PEC technique is proposed to clear the phase error when the output frequency approaches the target value. A discrete-time model by Verilog-A is built to verify the proposed PEC technique. Simulations have been carried out to prove that this technique can reduce at least 85% settling time as compared to the conventional PLL.