10nm FINFET technology for low power and high performance applications

Author

Guo, Di ; Shang, H. ; Seo, Kazuyuki ; Haran, B. ; Standaert, T. ; Gupta, Deepika ; Alptekin, E. ; Bae, D. ; Bae, G. ; Chanemougame, D. ; Cheng, K. ; Cho, Jeon-Wook ; Hamieh, B. ; Hong, Jonggi ; Hook, T. ; Jung, J. ; Kambhampati, R. ; Kim, Bumki ; Kim, Heo

Author_Institution

Albany Nanotechnol. Center, Albany, NY, USA

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um² SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; lithography; low-power electronics; CMOS platform technology; CPP; FinFET technology; MWF gate stack; RDF; SNM; SOI substrates; bulk substrates; contacted poly pitch; lithography; metallization pitch; multipatterning technology; multiworkfunction gate stack; optical patterning limits; random dopant fluctuation; self-aligned processes; size 10 nm; size 48 nm; static noise margin; variability degradation; voltage 0.75 V; voltage 140 mV; Abstracts; Logic gates; Metals; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021207

Filename

7021207