Memory usage reduction method for FFT implementations on DSP based embedded system

When computing large scale Discrete Fourier Transform (DFT) in an embedded system, the external memory will be filled with a great deal of signal and twiddle factor data. As the transform length grow, CPU cycle stall due to memory cache miss is increased because there is a lot of data to be fetch in an external memory. Thus, to reduce size of data is an important issue in embedded system. Since signal data is unknown, it cannot be compressed through mathematical relation, but twiddle factor can. According to the above problem, the method to reduce the size of twiddle factor and cache-optimized is proposed. This method uses the relationship between cosine and sine to minimize memory usage by twiddle factor, and optimize cache operation to enhance. As the result, the size of twiddle factor is reducing to almost 50% and has significant improvement when data size is great than cache size.