Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adoptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130 nm process shows 40% power savings with only 13% performance loss (due to adaptive clock stretching operations) and ~9.4% area overhead.