Integrated successive approximation register analog-to-digital converter for healthcare systems applications

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. The proposed a 1-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying SAR control logic that reduces half comparator and digital circuit power consumption, the provided SAR ADC achieves low power consumption. Measured results show that at the supply voltage of 1.0 V and sampling rate of 2 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 49.8 dB, a signal-to-noise and distortion ratio (SNDR) of 44.8 dB, an effective number of bits (ENOB) of 7.15 bits, a differential nonlinearity (DNL) of 0.39 LSB, an integral nonlinearity (INL) of 1.6 LSB and a power consumption of 40.2 μW.