DocumentCode
2416418
Title
A 180 Kbit Embeddable MRAM Memory Module
Author
Nahas, Joseph J. ; Andre, Torsten ; Subramanian, Chandrasekaran ; Lin, Huiming ; Alam, Syed M. ; Papworth, K. ; Martino, W.
Author_Institution
Freescale Semicond., Austin
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
791
Lastpage
794
Abstract
180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is also discussed.
Keywords
CMOS memory circuits; magnetic tunnelling; magnetoresistive devices; random-access storage; CMOS process; MRAM memory module; magnetic tunnel junction; magnetoresistive random access memory; size 0.28 micron; storage capacity 181 Kbit; CMOS process; Couplings; Driver circuits; Magnetic circuits; Magnetic separation; Magnetic tunneling; Magnetoresistance; Nonvolatile memory; Random access memory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405848
Filename
4405848
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