• DocumentCode
    2417418
  • Title

    Methodology to design reconfigurable architecture for acoustic algorithms

  • Author

    Chun Hok Ho ; Yiu, Cedric Ka Fai

  • Author_Institution
    Dept. of Comput., Imperial Coll. London, London, UK
  • fYear
    2009
  • fDate
    25-28 May 2009
  • Firstpage
    34
  • Lastpage
    35
  • Abstract
    This paper proposes a novel approach to implement reconfigurable architecture dedicated to acoustic algorithms. To explore different reconfigurable architecture suitable for acoustic algorithms, a methodology called virtual embedded block has been applied to identify suitable building blocks which can be a good candidate to embed into existing reconfigurable devices to increase the performance of the devices when acoustic computations are involved. Two acoustic algorithms, namely echo cancellation and beamforming, have been studied to demonstrate how this methodology applies to real life scenario. This methodology offers a rapid way to estimate how the embedded blocks in reconfigurable devices affect the performance of acoustic algorithms.
  • Keywords
    acoustic signal processing; array signal processing; echo suppression; embedded systems; field programmable gate arrays; reconfigurable architectures; FPGA; acoustic algorithms; beamforming; echo cancellation; field programmable gate array; reconfigurable architecture; virtual embedded block; Algorithm design and analysis; Consumer electronics; Design methodology; Liquefied natural gas; Neural networks; Next generation networking; Radio frequency; Reconfigurable architectures; US Department of Transportation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4244-2975-2
  • Electronic_ISBN
    978-1-4244-2976-9
  • Type

    conf

  • DOI
    10.1109/ISCE.2009.5157035
  • Filename
    5157035