• DocumentCode
    241801
  • Title

    Passivation of III–V oxide interfaces for CMOS

  • Author

    Robertson, John

  • Author_Institution
    Eng. Dept., Cambridge Univ., Cambridge, UK
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    High mobility semiconductors such as InGaAs or Ge are needed to continue CMOS scaling. However, the passivation of their surfaces has tended to leave too many interface gap states (Dit) which cause Fermi level pinning, and hinder the operation of the FET. The physical principles of improved passivation are explained, in terms of using gate dielectrics which include a diffusion barrier, and also valence control of the oxide next to the channel.
  • Keywords
    CMOS integrated circuits; Fermi level; III-V semiconductors; field effect transistors; gallium arsenide; germanium; indium compounds; interface states; passivation; CMOS scaling; FET operation; Fermi level pinning; Ge; III-V oxide interfaces; InGaAs; diffusion barrier; gate dielectrics; high mobility semiconductors; interface gap states; physical principles; surface passivation; valence control; Abstracts; Atomic measurements; Gallium arsenide; Logic gates; Passivation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021323
  • Filename
    7021323
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=241801