A FVF LDO regulator with damping-factor-control frequency compensation for SOC application

Author

Guoyi Yu ; Yelei Deng ; Xuecheng Zou ; Zhaoxia Zheng

Author_Institution

Sch. of Opt. & Electron. Inf., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

An output-capacitorless low-dropout regulator (OCL-LDO), which is based on flipped-voltage-follower (FVF) using damping-factor-control (DFC) frequency compensation for SOC application, is presented in this paper. The proposed LDO with 1.2V supply, 100mA load current was designed by SMIC 0.13um standard CMOS process. Simulation results have shown that the LDO can be stable for a load capacitance ranging from 0 to 80pF. The line regulation and load regulation are 3.3mV/V and 62uV/mA, respectively, and the quiescent current consumption is only 27uA. Under maximum load current changes, the overshoots and undershoots are less than 90mV and 140mV, and the recovery time is about 2.5us.

Keywords

CMOS integrated circuits; damping; frequency control; integrated circuit design; operational amplifiers; system-on-chip; DFC; FVF LDO regulator; OCL; SMIC standard CMOS process; SOC application; capacitance 0 pF to 80 pF; current 100 mA; current 27 muA; damping-factor-control frequency compensation; flipped-voltage-follower; load capacitance; output-capacitorless low-dropout regulator; size 0.13 mum; voltage 1.2 V; Current measurement; Damping; Regulators; Simulation; Solid state circuits; System-on-chip; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021407

Filename

7021407