Statistical timing macromodels of digital IP libraries

Author

Zanella, Stefano ; Neviani, Andrea ; Franzimi, B. ; Guardiani, Carlo

Author_Institution

Dipt. di Elettronica e Inf., Padova Univ., Italy

fYear

2000

fDate

2000

Firstpage

76

Lastpage

79

Abstract

In this paper we present an innovative statistical methodology that allows one to get an accurate, hierarchical macro-model of the probability density function (pdf) of digital IP block timings. Every timing measurement is expanded in series of orthogonal polynomials, and the coefficients of the expansion are directly obtained from the (known) moments of the pdf of SPICE model parameters. Good agreement is demonstrated by comparing the macro-model with traditional Monte-Carlo simulations on a 0.25 μm CMOS standard cell library

Keywords

CMOS integrated circuits; SPICE; integrated circuit modelling; polynomials; probability; statistical analysis; 0.25 mum; CMOS standard cell library; SPICE model parameters; digital IP block timings; digital IP libraries; hierarchical macro-model; orthogonal polynomials; probability density function; statistical methodology; statistical timing macromodels; Capacitance measurement; Integrated circuit modeling; Measurement standards; Polynomials; Probability density function; Propagation delay; SPICE; Semiconductor device modeling; Software libraries; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Metrology, 2000 5th International Workshop on

Conference_Location

Honolulu, HI

Print_ISBN

0-7803-5896-1

Type

conf

DOI

10.1109/IWSTM.2000.869316

Filename

869316