High data rate MDPSK receiver architecture for indoor wireless application

The paper presents a simulation study for a MDPSK (differential phase shift keying) receiver architecture suitable for short-range and high data rate indoor wireless applications. The proposed architecture comprises a coarse frequency correction (CFC) block, a timing recovery block, a channel estimation block, a carrier recovery block and an equalizer block. The CFC block is based on a data aided approach and the timing recovery uses a simple correlator which also doubles up as a channel estimator. The carrier recovery block based on a second order loop is used to remove the residual carrier offset. The equalizer uses a decision feedback equalizer (DFE) structure that is initialized with a "one-shot" tap coefficient estimate computed from the channel estimate. This architecture is especially well suited for next generation Bluetooth applications (Radio2) where the proposed modulation is expected to be a 2/4/8DPSK signaling scheme. This architecture supports a symbol rate of 4Mbaud/sec which can potentially increased the capacity of existing Bluetooth radio (V1.1) by up to 12 times.