Novel 2T gain cell with enhanced retention time for embedded DRAM application

Author

Hui Li ; Yinyin Lin ; Huang, R. ; Lijun Song ; Qingtian Zou ; Jingang Wu

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

A high performance 2T gain cell memory device is demonstrated for the first time in 0.13μm CMOS technology. A novel asymmetric source and drain doping profile combined with high threshold voltage (Vt) scheme for the write transistor is introduced to reduce the cell leakage and then improve data retention characteristics. Experimental results show a data retention of 698μs @85°C with 99.9% yield, which proves that the proposed 2T gain cell may be a very promising candidate for low cost and high density eDRAM application.

Keywords

CMOS memory circuits; DRAM chips; semiconductor doping; CMOS technology; asymmetric source; cell leakage; data retention characteristics; drain doping profile; embedded DRAM; enhanced retention time; high density eDRAM; high performance 2T gain cell memory device; high threshold voltage scheme; low cost eDRAM; size 0.13 mum; temperature 85 degC; time 698 mus; write transistor; Abstracts; CMOS integrated circuits; CMOS technology; Doping; Fabrication; Junctions; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021626

Filename

7021626