CU seed, CMP process development and via resistance extraction in through silicon via technology

Author

Zheng-Jun Hu ; Xin-Ping Qu ; Hong Lin ; Ren-Dong Huang ; Qing-Yun Zuo ; Ming Li ; Shou-Mian Chen ; Yu-Hang Zhao

Author_Institution

State key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

Through Silicon Via (TSV) is now becoming one of the most critical and enabling technologies for 3-D integration.Vertical interconnection of several chips offered by TSV will result in improved performance and functionality, miniaturization in size and weight and reduced power consumption. Cu as TSV filling material is well used in the traditional damascene process. In this work, Cu seed deposition in high aspect ratio features using traditional PVD tool is developed and seamless TSV Cu filling is achieved. The TSV via dishing in Cu CMP soft landing step is also discussed. Finally, the TSV via resistance is extracted from the special designed test structure without additional bonding wafer or backside patterning.

Keywords

chemical mechanical polishing; copper; electric resistance; integrated circuit interconnections; three-dimensional integrated circuits; 3D integration; CMP process development; Cu; TSV filling material; copper seed deposition; high aspect ratio features; resistance extraction; through silicon via technology; vertical interconnection; Abstracts; Bonding; Resistance; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021634

Filename

7021634