A wafer-scale FFT processor featuring a repeatable building block

Author

Yamashita, Koichi ; Kanasugi, Akinori ; Hijiya, Shimpei ; Goto, Gensuke

Author_Institution

Fujitsu Lab. Ltd., Atsugi, Japan

fYear

1989

fDate

3-5 Jan 1989

Firstpage

299

Lastpage

307

Abstract

The wafer-scale 170000-gate fast Fourier transform (FFT) processor has three features: a single repeatable building block containing a processing element (PE) and its interconnects, mask-programmable routing by the placement of contact holes, and a built-in self-test (BIST) for the PE and its interconnects. The wafer system is composed of 48 PEs selected out of a total of 88 PEs. The PE consists of a 2800-gate multiplier-accumulator and 700-gate BIST circuitry. The processor performs parallel 16-bit, 8-point complex FFT and is implemented with 725 I/O pads in triple-metal 2.3-μm CMOS technology on a 4-inch wafer. This wafer is mounted face down on an 11.8×11.8-cm² substrate by solder bumps

Keywords

CMOS integrated circuits; fast Fourier transforms; microprocessor chips; 16 bit; 2.3 micron; BIST circuitry; CMOS technology; built-in self-test; contact holes; mask-programmable routing; multiplier-accumulator; placement; processing element; repeatable building block; triple metal; wafer system; wafer-scale FFT processor; Built-in self-test; CMOS technology; Circuit faults; FETs; Fast Fourier transforms; Integrated circuit interconnections; Laser beam cutting; Nonvolatile memory; Redundancy; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9901-9

Type

conf

DOI

10.1109/WAFER.1989.47560

Filename

47560