DocumentCode
2426604
Title
On the design of a selftesting WSI multiplier array
Author
Ramacher, Ulrich ; Beichter, Jorg ; Kamp, Winfried
Author_Institution
Siemens AG, Munich, West Germany
fYear
1989
fDate
3-5 Jan 1989
Firstpage
309
Lastpage
316
Abstract
The design of a 6.8×6-cm wafer-scale integration (WSI) chip for matrix-matrix multiplication, the layout, and its verification hierarchy are described. The chip is designed in a defect-tolerant style. Whole wafer lithography resulting in 2-μm effective design rules was chosen because of reduced costs of masks
Keywords
VLSI; cellular arrays; lithography; multiplying circuits; 2 micron; costs; defect-tolerant style; effective design rules; layout; masks; matrix-matrix multiplication; selftesting WSI multiplier array; verification hierarchy; wafer-scale integration; whole wafer lithography; Built-in self-test; Computer architecture; Costs; Laboratories; Lithography; Multiplexing; Switches; Systolic arrays; Testing; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47561
Filename
47561
Link To Document