DocumentCode
2429625
Title
Switching noise due to internal gates: delay implications and modeling
Author
Casimiro Gomez, G. ; Cadena, Alfonso ; Champac, Victor H.
Author_Institution
Dept. of Electron. Eng., Nat. Inst. of Astrophys. Opt. & Electron., Puebla, Mexico
fYear
2000
fDate
2000
Abstract
In this paper the ground bounce due to switching of internal CMOS gates is analyzed. The implications of the switching noise on the delay of the switching gates are analyzed. A novel analytical model to estimate the switching noise due to internal logic is proposed. A good agreement has been found between the proposed analytical model with HSpice simulations
Keywords
CMOS logic circuits; SPICE; circuit simulation; delays; integrated circuit modelling; integrated circuit noise; logic gates; logic simulation; HSpice simulations; analytical model; delay implications; ground bounce; internal CMOS gates; internal logic; modeling; switching noise; Analytical models; CMOS technology; Delay; Inductance; Integrated circuit noise; Integrated circuit technology; Optical noise; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on
Conference_Location
Cancun
Print_ISBN
0-7803-5766-3
Type
conf
DOI
10.1109/ICCDCS.2000.869819
Filename
869819
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