Shift add approach based implementation of RNS-FIR filter using modified product encoder

In this work, two approaches to realize a finite impulse response (FIR) filter using residue number system (RNS) are proposed. The proposed implementations take advantage of shift and add approach offered by the chosen moduli set. Both the architecture were implemented using gate level Verilog HDL and are synthesized using Cadence RTL compiler in UMC 90 nm technology. The performance of the filters are compared in terms of area, power, and delay with an earlier proposed version of reconfigurable RNS FIR filter. The functionality of the filters were verified using Altera DSP Builder. These designs also uses a modified product encoder to optimize the filter performance. Results show that one of the proposed architecture significantly improves the delay, while the second approach minimizes power and area. Both implementations offer advantage in area-delay AT and power-delay-product PTP.