Optimized design of digital filter in Sigma-Delta A/D converter

A multi-stage digital decimator for sigma-delta analog-to-digital converter with an oversampling ratio of 64 is described. To optimize the architecture of the digital filters and the circuit implementation, multi-rate multi-stage decimation, half-band filter and multiplier sharing are used. The filter is designed and simulated using SIMULINK and MATLAB while the hardware realization is obtained using FPGA Xilinx technology. A significant hardware reduction of 35% over the conventional approach is achieved, the cost and power dissipation are reduced as well. The SNR of the filter output is 99 dB, reaching the requirement for 16-bit resolution.