Embedded hardware architectures for scale and rotation invariant feature detection

Scale Invariant Feature Transform is used in many computer vision algorithms like object recognition, motion tracking and stereo matching to name a few. Since the technique is computationally complex, designing low cost embedded architectures to meet real-time constraints is a challenge. To meet this challenge, we propose to use a FPGA-DSP integrated platform. SIFT is divided into two major stages: keypoint detection and descriptor generation. The descriptor generation is implemented using an ARM Cortex based DSP. The more computationally intensive stage of keypoint detection is implemented on the FPGA. In this paper, we present novel, efficient, scalable architectures for the keypoint detection step. The architectures are based on parallelizable and pipelined computational flow. The three designs incorporate a Look Up Table based approach, which makes the use of multipliers obsolete in scale space generation stage. The architectures reduce the time taken for keypoint detection by more than 54%, 91% and 88% respectively as compared to existing designs.