• DocumentCode
    243215
  • Title

    Parallel hardware architecture and FPGA implementation of a differential evolution algorithm

  • Author

    Jewajinda, Yutana

  • Author_Institution
    Sch. of Eng. & Ind. Technol., Dept. of Electr. Eng., Silpakorn Univ., Nakornpathom, Thailand
  • fYear
    2014
  • fDate
    22-25 Oct. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents a parallel hardware architecture and FPGA implementation of a differential evolution (DE) algorithm. Due to inherently parallelism in DE algorithms, parallel hardware implementation can provide speed up over traditionally software implementation. The performance evaluation is performed by comparing execution time between the proposed FPGA implementation and sequential software implementations on multi-core processors.
  • Keywords
    evolutionary computation; field programmable gate arrays; mathematics computing; multiprocessing systems; parallel architectures; DE algorithm; FPGA implementation; differential evolution algorithm; field programmable gate array; multicore processor; parallel hardware architecture; parallel hardware implementation; software implementation; FPGA; differential evolution; hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2014 - 2014 IEEE Region 10 Conference
  • Conference_Location
    Bangkok
  • ISSN
    2159-3442
  • Print_ISBN
    978-1-4799-4076-9
  • Type

    conf

  • DOI
    10.1109/TENCON.2014.7022429
  • Filename
    7022429
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=243215